1. Field of the Invention
The invention relates in general to a structure of a conductive wiring layer. More particularly, the invention relates to a structure of a conductive wiring layer under bonding pads of a chip.
2. Description of the Related Art
Recently, semiconductors have been widely applied as the flourish development of electronic industry. The booming electronic industry thus evokes a fast growth of semiconductor fabrication technique. The semiconductor fabrication process can be divided into a front-end process and a back-end process. In the front-end process, the semiconductor substrate and the semiconductor device are formed. That is, the front-end process involves single crystal and epitaxy growing technique, and MOS and interconnection fabrication techniques. The back-end process basically includes the package process. The objective of package is to prevent the die from being affected by the moisture, heat and noise. The package further provides the signal connection between the die and the substrate to facilitate functioning and testing. The wire bonding process in the package process is to bond each electrical contact, that is, a bonding pad on the chip, to a terminal of the carrier with a very fine gold wire. Thereby, the electric signal of the integrated circuit is transmitted to external.
In the wire bonding process, the welding has to be enhanced with ultra-sonic vibration, such that the area under the bonding pad is experienced a very large impact to cause breakage or fracture of the fragile dielectric layers between metal layers. The disconnected neighboring conductive wiring layers are thus abnormally connected together due to the formation of undesired contact or electrical open. The abnormal electrical connection is not allowed in the original circuit design. That is, the abnormal electrical connection destructs the original circuit design to cause the chip failure, and to waste the fabrication cost.
In addition to the input/output signal contacts, the power contacts and ground contacts are crucial to a semiconductor chip. The power contact is used as a current input terminal to provide the current required for the operations of circuit devices in the chip. The current is grounded in external via the ground contact. Therefore, the traces connected to the power contact and the ground contact should have a total cross sectional area sufficiently large to allow the required current to flow through. If a massive amount of current is flowing through a conductive wire with insufficient cross sectional area, the metal conductive wiring layer will be blown to damage the chip. Therefore, the power and ground traces require a larger cross sectional area. As the conductive wiring layer in the semiconductor chip is made of thin film with a constant thickness, the cross sectional area thereof can be increased by way of increasing the width of the conductive wiring layer.
FIG. 1 and FIG. 2 show a top view and a side view of a chip and a part of carrier. The chip 10 comprises a core circuit 12 and a peripheral bonding pad area 14. The bonding pad area 14 comprises a plurality of bond pads 16, which are formed by the exposed openings on the uppermost conductive wiring layer (not shown). The bonding pads 16 are connected to the power ring 24, the ground ring 22 and the finger contact 26 of the carrier 20 by bonding wires 30. The allocation of the bonding pads 16 is shown as the first row 41 and the second row 42 of the bonding pads.
In FIG. 3, an enlarged view of the boundary between the core circuit and the bonding pad area is shown. In FIG. 4, a cross-sectional view cutting along the line I—I of FIG. 3 is illustrated. The chip 10 has a layer of substrate 18. A conventional conductive wiring layer structure 100 is located on the substrate 18. The conductive wiring layer structure 100 is formed by alternately overlaying three conductive wiring layers 110, 130 and 150 with three dielectric layers 120, 140 and 160. In this structure, an insulating layer 40 is formed on the uppermost conductive wiring layer 102.
On the conductive wiring layer structure 100, a part of the insulation layer 40 is removed to form a plurality of openings (that is, the bonding pads 16) above the conductive wiring layer 112 to provide contacts for external electric connections. The bonding wires 30 include the gold wires 32 and the gold balls 34. In the wiring bonding process, the bonding machine bonds the wires 30 on the bonding pads 16 of the chip 16 to form gold balls 34 and to pull out the gold wires 32, which selectively connect with the ground ring 22, the power ring 24 and the finger contact 26 as shown in FIG. 1. The surface area of the bonding pads 16 is larger than the effective area of the gold balls 34 to avoid the contact between the gold balls 34 and the insulation layer 40.
However, in the conventional conductive wiring structure 100, due to a great impact pressure caused by wiring bonding, the dashed line part of the fragile dielectric layers 120, 140 and 160 are easily damaged and fractured to cause a deformation among the metal conductive wiring layers 110, 130 and 150. As a result, abnormal contacts are formed between these metal conductive wiring layers 110, 130 and 150 to cause abnormal electric connection. The original circuit design of the chip 10 is thus failed.
FIG. 5 is a simplified drawing of FIG. 4. In FIG. 5, only the conductive wiring layer 100 is shown. The conductive wiring layer is divided into a wide conductive wiring region 101 and a narrow conductive wiring region 102 according to the width of the conductive wire. The power trace requires a larger cross section to carry sufficient current, so as to avoid the metal conductive wiring layer to from blowing out. Referring to FIGS. 1 and 2, according to the requirement of design, the bonding pads 16 to connect the power source located near the ground ring 22. Referring to FIG. 3, the bonding pads 16 in the lower part are restricted to trace through the narrow conductive wiring region 102. Such conductive wires have insufficient width. As shown in FIG. 5, even vias are formed for connecting multi-layers of the traces to increase the total trace width, the total width is neither sufficient. For example, assume that the width of each conductive trace in the narrow conductive wiring region 102 is 20 units, and the required total width is 100 units, 60 units is obtained by adding the widths for three conductive wires. It is still insufficient. Therefore, while the current flows through, an overheat phenomenon to blow out the conductive trace is still possible.
According to the above, the conventional conductive wiring structure under the bonding pad of a chip has the following disadvantages:
(1) The prior art cannot provide sufficiently width of conductive wires for the power and ground bond pads of the chip. Therefore, the conductive wiring layer is easily blown out.
(2) During the wire bonding process, the bonding process causes a great impact to break or crash the dielectric layers under the bonding pad, so that undesired electric contacts are formed due to the extrusion of conductive wires.